期刊
IEEE TRANSACTIONS ON ELECTRON DEVICES
卷 68, 期 8, 页码 4004-4009出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2021.3091952
关键词
Logic gates; MOSFET; Ions; Transient analysis; Simulation; Neck; Silicon; Heavy ion; power metal-oxide-semiconductor field effect transistor (MOSFET); single-event burnout (SEB); single-event effect (SEE); single-event gate rupture (SEGR); single-event hardening; super-junction (SJ); technology computer-aided design (TCAD) simulation
资金
- Defense Threat Reduction Agency (DTRA) [HDTRA1-17-1-0038]
This study introduces a design for a 650V super-junction power MOSFET that enhances tolerance to SEB and SEGR. Experimental measurements validate the design accuracy, showing that the trench gate SJ device design improves survivability to SEGR.
This article presents design for a 650-V super-junction (SJ) power metal-oxide-semiconductor field effect transistor (MOSFET) which improves tolerance to both single-event burnout (SEB) and single-event gate rupture (SEGR). Experimental measurements of SEGR in a generic commercial planar gate SJ device are used to validate the accuracy of the design. In an SJ device with a planar gate, reducing the neck width improves the tolerance to gate rupture but significantly changes the electrical device characteristics. The trench gate SJ device design is shown to overcome this problem. A buffer layer and larger P+-plug are added to the trench gate SJ power transistor to improve SEB tolerance. The proposed trench gate structure improves the SEGR survivability by a factor of 10.
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