Short-Channel Top-Gate InGaZnO Thin-Film Transistors Fabricated With Boron Implantation Into Source/Drain Regions

In this brief, we discuss top-gate InGaZnO thin-film transistors (InGaZnO TFTs) fabricated with boron (B) implantation into the source-drain regions, focusing on channel shortening. B was implanted through the gate insulator into the InGaZnO layer. From scanning capacitance microscopy (SCM) analysis, we found that boron implantation in the S/D regions of InGaZnO TFTs induces channel shortening. We also found that such channel shortening is suppressed by optimizing acceleration voltage in the boron implantation process, leading to good operation in short-channel (1.5 mu m) InGaZnO TFT.

Automated summary

In this study, top-gate InGaZnO thin-film transistors with boron implantation in the source-drain regions were discussed, focusing on channel shortening. It was found that boron implantation induced channel shortening in InGaZnO TFTs, but optimizing the acceleration voltage in the implantation process could suppress this effect, leading to good operation in short-channel InGaZnO TFTs.