期刊
IEEE MICRO
卷 41, 期 4, 页码 58-66出版社
IEEE COMPUTER SOC
DOI: 10.1109/MM.2021.3085537
关键词
Sockets; Program processors; Computer architecture; Open source software; Linux; Skeleton; Hardware
资金
- Defense Advanced Research Projects Agency (DARPA) through the Circuit Realization at Faster Timescales (CRAFT) Program [HR0011-16-C0052]
- Advanced Research Projects Agency-Energy (ARPA-E), U.S. Department of Energy [DE-AR0000849]
- NSF CCRI Award [2016662]
- ADEPT Lab
- Direct For Computer & Info Scie & Enginr [2016662] Funding Source: National Science Foundation
- Division Of Computer and Network Systems [2016662] Funding Source: National Science Foundation
The open-source hardware community offers a variety of processors and accelerators, but effectively combining them into a complete SoC remains a challenge. Researchers have proposed a design flow for evaluating the seamless integration of accelerators into a complete SoC through rapid FPGA prototyping.
The open-source hardware community contributes a variety of processors and accelerators, but combining them effectively into a complete System-on-Chip (SoC) remains a difficult task. We present a design flow for the seamless hardware and software integration of accelerators into a complete SoC and for its evaluation through rapid FPGA-based prototyping. By leveraging ESP, our open-source platform for agile heterogeneous SoC design, we demonstrate FPGA prototypes of various SoC designs, featuring the NVIDIA Deep Learning Accelerator and the Ariane RISC-V 64-bit processor core.
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