期刊
IEEE JOURNAL OF SOLID-STATE CIRCUITS
卷 56, 期 7, 页码 2040-2053出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2021.3073068
关键词
Noise measurement; Qubit; Cryogenics; Logic gates; Bandwidth; Quantum capacitance; Impedance; Capacitive loading; cryogenic CMOS; low noise amplifier (LNA); noise reduction; quantum computing; qubit readout; transformer
资金
- European Union [688539]
This study presents a cryogenic broadband low noise amplifier (LNA) for quantum applications based on a standard 40-nm CMOS technology, achieving broadband input matching impedance and low noise figure, while demonstrating sub-1 dB noise figure at 4.2 K temperature.
A cryogenic broadband low noise amplifier (LNA) for quantum applications based on a standard 40-nm CMOS technology is reported. The LNA specifications are derived from the readout of semiconductor quantum bits at 4.2 K, whose quantum information signals are characterized as phase-modulated signals. To achieve broadband input matching impedance and low noise figure, the gate-to-drain capacitance of the input transistor is exploited. The goal is to involve a resistive and capacitive load into the input impedance match of a common-source stage with source inductive degeneration. The capacitive load is created by an LC parallel tank whose resonant frequency is lower than the operating frequency. The achieved non-constant in-band equivalent capacitance is proven to be beneficial to input impedance matching. The resistive part of the load is provided by the transconductance of the cascode stage implicitly. An inductor is added to the gate of the cascode transistor to suppress its noise, and a transformer-based resonator with two resonant frequencies serves as the load of the first stage, thus extending the operating bandwidth. Design considerations for the cryogenic temperature operation of the LNA are proposed and analyzed. The LNA achieves a measured gain (S-21) of 35 +/- 0.5 dB, return loss > 12 dB, and NF of 0.75-1.3 dB across the band (4.1-7.9 GHz), with 51.1-mW power consumption at room temperature, while it shows a measured gain of 42 +/- 3.3 dB, and NF of 0.23-0.65 dB with 39-mW power consumption at 4.2 K between 4.6 and 8 GHz. To the best of our knowledge, this is the first report of a cryogenic LNA based on a bulk CMOS process working above 4 GHz showing sub-1-dB NF both at room and cryogenic temperatures.
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