Stacked-Interconnect for Monolithic Integration of Low-Temperature Polysilicon and Amorphous Metal-Oxide Thin-Film Transistors

While offering a range of practical benefits, the monolithic integration of low-temperature polysilicon (LTPS) and amorphous metal-oxide thin-film transistors presents several incompatibility issues regarding materials and processes. Presently addressed are two critical ones arising from the back-end processes of contact treatment and metallization. Both are resolved by employing a stacked-interconnect consisting of two conductor layers, with each layer forming the preferred contact electrodes for one of the two types of transistors. At the expense of a slight increase in process complexity, a narrow distribution of low specific contact resistance (similar to 10(-5) Omega.cm(2)) for both types of transistors was obtained, thus giving rise to more consistent transistor characteristics. Inverters consisting of complementary top-gate LTPS pull-up and bottom-gate indium-gallium-zinc oxide pull-down transistors were demonstrated, exhibiting a gain of 40 V/V and a rail-to-rail full swing.

Automated summary

The incompatibility issues of materials and processes for the monolithic integration of low-temperature polysilicon (LTPS) and amorphous metal-oxide thin-film transistors are addressed by using a stacked-interconnect technique, resulting in low specific contact resistance for both transistors. This approach allows for more consistent transistor characteristics and enables the demonstration of inverters with a gain of 40 V/V and rail-to-rail full swing.