The Impacts of Ferroelectric and Interfacial Layer Thicknesses on Ferroelectric FET Design

Despite tremendous interests in ferroelectric field-effect transistors (FEFETs) for embedded, data-centric applications, the fundamental trade-offs between memory window (MW) and write voltage to optimize performance remains poorly understood. To that end, we fabricated ferroelectric (FE) ZrO2 based, p-type FEFETs and studied the impacts of FE and the interfacial oxide layer (IL) thicknesses (t(FE) and t(IL), respectively) on device performance. We observe that a decrease of t(FE) and t(IL) reduces not only write voltages for erasing and programming, but also the memory window. A quantitative analysis of these results offers the following insights and guidelines for FEFET design: to decrease write voltages, all of t(FE), t(IL) and coercive field of FE needs to decrease, and to compensate for the subsequent decrease in MW, the polarization of the FE needs to be increased - not with standing the fact that the reliability implications of the magnitude of FE polarization still need to be understood.

Automated summary

In this study, ferroelectric ZrO2-based p-type FEFETs were fabricated and the impact of ferroelectric and interfacial oxide layer thickness on device performance was investigated. The results showed that decreasing thickness reduces write voltages and memory window.