4.8 Article

Can Carbon Nanotube Transistors Be Scaled Down to the Sub-5 nm Gate Length?

期刊

ACS APPLIED MATERIALS & INTERFACES
卷 13, 期 27, 页码 31957-31967

出版社

AMER CHEMICAL SOC
DOI: 10.1021/acsami.1c05229

关键词

carbon nanotube; field-effect transistor; gate-all-around; first principle; quantum transport simulation

资金

  1. National Key Research & Development Program [2016YFA0201901, 2016YFB0700600, 2017YFA206303]
  2. National Natural Science Foundation of China [11674005, 91964101]

向作者/读者索取更多资源

Single-walled carbon nanotubes have shown promising potential as a semiconductor for future transistors and integrated circuits due to their thin channel thickness and high injection velocity. By exploring the performance limits of CNT FETs based on a gate-all-around structure, it has been found that they can achieve high-performance targets and have superior energy-delay products compared to other materials at sub-5 nm gate lengths. However, despite the theoretical possibility of scaling CNT FET gate lengths to 2 nm, the ultimate limit is considered to be at 5 nm due to the tradeoff between performance and power consumption.
Single-walled carbon nanotubes (CNTs) have been considered as a promising semiconductor to construct transistors and integrated circuits in the future owing to their ultrathin channel thickness and ultrahigh injection velocity. Although a 5 nm gate-length CNT field-effect transistor (FET) has already been experimentally fabricated and demonstrates excellent device performance, the potential or constraint factors on performance have not been explored or revealed. Based on the benchmark of the device performance between the experimental and simulated 5 nm gate-length CNT FETs, we use the first-principles quantum transport approach to explore the performance limit of CNT FETs based on the gate-all-around (GAA) device geometry for the first time. It is found that the GAA CNT FETs can fulfill the ITRS 2028 high-performance target in the 2 nm gate-length node in terms of the on-state current, delay time, and power consumption. We also find that the energy-delay product of the CNT FETs is superior to those of the high-performance 2D materials and Si Fin FETs at the sub-5 nm gate length due to its unique electrical property. Though theoretically the gate length of CNT FETs can be potentially scaled to 2 nm, considering the tradeoff between the performance and power consumption, 5 nm is the ultimate scaled limit.

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