Investigations on Electrical Parameters Degradations of p-GaN HEMTs Under Repetitive UIS Stresses

Electrical parameters degradations of p-GaN high-electron-mobility transistors (HEMTs) under repetitive unclamped-inductive-switching (UIS) stresses have been investigated in this article. With the help of the TCAD simulations, the experimental frequency-dependent conductance analyses (G(p)/omega), and the experimental capacitance analyses (C-ds), it is demonstrated that the trapping effects near the gate region and in the gate to drain access region dominate the degradations. Due to the extremely high-voltage bias during UIS stresses, the trapping of electrons happens near gate region, resulting in the positive shifts of threshold voltage (V-th), the degradations of ON-state resistance, the reductions of the gate leakage current, and the reductions of OFF-state leakage current (I-dss). Two experimental methods, the C-ds analyses and the G(p)/omega analyses, are introduced to characterize the trapping effects in p-GaN HEMT for the first time. Nonetheless, the large current surging during UIS stresses enhances the impact ionization and leads to the increase in I-dss. The analyses above have been validated by the TCAD simulation successfully. For switching parameters, such as the voltage rises/falls time, which should be considered when designing power electronic systems, the increase in V-th induced by the UIS stresses dominates the changes.

Automated summary

This study investigates the electrical parameter degradations of p-GaN HEMTs under repetitive UIS stresses, demonstrating that trapping effects near the gate region dominate the degradation. The experimental methods and TCAD simulations validated the findings, showing that the trapping effects have a significant impact on device performance.