期刊
NEURAL COMPUTING & APPLICATIONS
卷 33, 期 18, 页码 11753-11764出版社
SPRINGER LONDON LTD
DOI: 10.1007/s00521-021-05817-x
关键词
Spiking neural networks; Neuromorphic computing; Networks-on-chip; Deflection routers
资金
- National Natural Science Foundation of China [61976063]
- Overseas 100 Talents Program of Guangxi Higher Education
- Guangxi Key Lab of Multi-source Information Mining Security [19-A-03-02]
- Guangxi Key Laboratory of Wireless Wideband Communication and Signal Processing
- Young and Middle-aged Teachers' Research Ability Improvement Project in Guangxi Universities [2020KY02030]
- Diecai Project of Guangxi Normal University
This study introduces a minimally buffered deflection router (MBDR) to address the scalability challenge of hardware SNNs, which reduces energy consumption and costs while maintaining a high level of system throughput through the use of deflection router technique and a novel flow controller.
Spiking neural networks (SNNs) have the potential to closely mimic the information processing of biological brains, by using massive neurons that are interconnected in a complex network. Recent researches have considered using electronic hardware circuits to SNN implementations to meet real-time processing requirements. Network-on-Chips (NoCs) have been widely used to develop such SNN circuits as their interconnections can offer stable interconnectivity for neuron communications with high throughput and real-time execution. However, its scalability is limited due to expensive and complex NoC routers which leads to high energy consumption and large area utilization. Therefore, a minimally buffered deflection router (MBDR) is proposed in this work to address the scalability challenge of the hardware SNNs. It employs a deflection router technique to remove most of the inter-buffers and other expensive components of the conventional routers. Moreover, a novel flow controller is developed in MBDR to further reduce power consumption. Compared to existing approaches, experimental results show that based on 90-nm CMOS technology the area and power consumption of the proposed router are reduced by similar to 86% and similar to 88%, respectively. In the meantime, system throughput is maintained at a high level.
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