Impact of interface trap charges on electrical performance characteristics of a source pocket engineered Ge/Si heterojunction vertical TFET with HfO2/Al2O3 laterally stacked gate oxide

This work reports the impact of interface trap charges (ITCs) on the electrical performance characteristics of a source pocket engineered (SPE) Ge/Si heterojunction (HJ) vertical TFET (V-TFET) with an HfO2/Al2O3 laterally stacked heterogeneous gate oxide (LSHGO) structure. SILVACO ATLAS (TM) 3-D TCAD tool has been used to compare various electrical performance parameters which includes DC parameters (i.e. I-ON, I-OFF, I-ON/I-OFF and subthreshold swing), RF figures of merit (i.e. transconductance, output conductance, cut-off frequency, the maximum frequency of oscillation, transit time, gain bandwidth product, transconductance generation factor (device efficiency) and transconductance frequency product) and linearity figures of merit (i.e. g(m2), g(m3), Third order voltage intercept point (VIP3), third intercept input power (IIP3), third order intermodulation distortion power (IDM3), 1-dB compression point and zero crossover point (ZCP)) of the proposed Ge/Si SPE-HJ-LSHGO-VTFET with their corresponding values of SPE-HJ-V-TFET with only Al2O3 as the gate oxide for both donor (+ve) and acceptor (-ve) interface trap charges at the gate oxide/channel interface. The reported study shows that the proposed HfO2/Al2O3 based SPE-HJ-LSHGO-V-TFET device is more immune to ITCs than the SPE-HJ-V-TFET device with only Al2O3 as the gate oxide.

Automated summary

This study compares the impact of different gate oxide structures and interface trap charges on the electrical performance parameters of source pocket engineered Ge/Si heterojunction vertical TFET devices. The results show that devices based on HfO2/Al2O3 have better immunity to ITCs.