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Neda Talebipour et al.
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Subhendu Kumar Sahoo et al.
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Narges Hajizadeh Bastani et al.
JOURNAL OF NANOELECTRONICS AND OPTOELECTRONICS (2017)
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Geunho Cho et al.
INTEGRATION-THE VLSI JOURNAL (2016)
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Atiyeh Panahi et al.
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Sneh Lata Murotiya et al.
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Sneh Lata Murotiya et al.
INTERNATIONAL JOURNAL OF ELECTRONICS (2014)
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Supriya Karmakar et al.
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Mohammad Hossein Moaiyeri et al.
IET COMPUTERS AND DIGITAL TECHNIQUES (2013)
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Mohammad Hossein Moaiyeri et al.
INTERNATIONAL JOURNAL OF ELECTRONICS (2012)
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IEEE TRANSACTIONS ON NANOTECHNOLOGY (2011)
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M. H. Moaiyeri et al.
IET CIRCUITS DEVICES & SYSTEMS (2011)
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Keivan Navi et al.
INTEGRATION-THE VLSI JOURNAL (2011)
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K. You et al.
MICRO & NANO LETTERS (2011)
A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application - Part I: Model of the intrinsic channel region
Jie Deng et al.
IEEE TRANSACTIONS ON ELECTRON DEVICES (2007)
A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application - Part II: Full device model and circuit performance benchmarking
Jie Deng et al.
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Carbon nanotube field-effect transistors for high-performance digital Circuits - DC analysis and modeling toward optimum transistor structure
Arijit Raychowdhury et al.
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High performance n-type carbon nanotube field-effect transistors with chemically doped contacts
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NANO LETTERS (2005)
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