Approximate Full Adders for Energy Efficient Image Processing Applications

This paper proposes six novel approximate 1-bit full adders (AFAs) for inexact computing. The six novel AFAs namely AFA1, AFA2, AFA3, AFA4, AFA5, and AFA6 are derived from state-of-the-art exact 1-bit full adder (EFA) architectures. The performance of these AFAs is compared with reported AFAs (RAAs) in terms of design metrics (DMs) and peak-signal-to-noise-ratio (PSNR). The DMs under consideration are power, delay, power-delay-product (PDP), energy-delay-product (EDP), and area. For a fair comparison, the EFAs and proposed AFAs along with RAAs are described in Verilog, simulated, and synthesized using Cadences' RC tool, using generic 180 nm standard cell library. The unconstrained synthesis results show that: among all the proposed AFAs, the AFA1 and AFA2 are found to be energy-efficient adders with high PSNR. The AFA1 has a total power = 1.722 mu W, delay = 213 ps, PDP = 0.3668 fJ, EDP = 78.1285 x 10(-27) Js, area = 36.59 mu m(2), and PSNR = 26.4292 dB. And the AFA2 has the total power = 1.924 mu W, delay = 215 ps, PDP = 0.4136 fJ, EDP = 88.924 x 10(-27) Js, area = 33.264 mu m(2), and PSNR = 26.4292 dB.

Automated summary

This paper introduces six novel approximate 1-bit full adders (AFAs) for inexact computing, derived from state-of-the-art exact 1-bit full adder (EFA) architectures. Performance comparison with reported AFAs (RAAs) shows that AFA1 and AFA2 are energy-efficient adders with high PSNR among all the proposed AFAs.