A read-disturb-free and write-ability enhanced 9T SRAM with data-aware write operation

This paper presents a single-ended 9T SRAM cell with data-aware write-word-line structure to improve write ability, and a positive feedback sense amplifier (SA) to solve sensing challenge at an ultra-low voltage. The proposed 9T cell is well suited for bit-interleaving architecture in SRAM array. Simulation results indicate that at a 0.5 V supply voltage, the proposed SRAM cell achieves the same read static noise margin (RSNM) as that of conventional 8T SRAM cell, because the read-decoupled read buffer achieves read-disturb-free operation. While at the same supply voltage, its write margin (WM) is 2.68x compared with the 8T SRAM cell. As a result, a lower minimum operation voltage is achieved. Additionally, its leakage power consumption is reduced by 86.1% compared with the 8T SRAM cell in the 40-nm standard CMOS technology, TT corner, 25 degrees C.

Automated summary

This paper introduces a novel 9T SRAM cell with a data-aware write-word-line structure and a positive feedback sense amplifier to enhance write ability and address sensing challenges at ultra-low voltages. Simulation results demonstrate that the proposed cell achieves comparable read performance to the conventional 8T SRAM cell at 0.5V supply voltage, while significantly improving write margin. This design also leads to a substantial reduction in leakage power consumption compared to the 8T SRAM cell in a 40nm standard CMOS technology.