期刊
IEEE TRANSACTIONS ON POWER ELECTRONICS
卷 36, 期 4, 页码 4006-4015出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TPEL.2020.3023770
关键词
Feature extraction; Power quality; Real-time systems; Harmonic analysis; Training; Pattern recognition; Entropy; Deep convolutional neural network (DCNN); field-programmable gate array (FPGA); power quality events (PQEs); random vector functional link network; real-time analysis; self-adaptive variational mode decomposition (SAVMD)
This article introduces a method that combines SAVMD, DCNN, and OSRVFLN for real-time categorization of power quality events. The method optimizes the number of decompositions and data-fidelity factor to extract efficient features, automatically extracts discriminative features using DCNN, and trains a feature vector with OSRVFLN classifier to achieve maximum classification accuracy.
In this article, self-adaptive variational mode decomposition (SAVMD), deep convolutional neural networks (DCNN), and online-sequential random vector functional link networks (OSRVFLN) are integrated to categorize the single as well as combined power quality events (PQEs) in real time. The SAVMD method is proposed to optimize both the number of decomposition and data-fidelity factor to extract the most efficient band-limited mode (BLM) based on entropy and Kurtosis index. The most discriminative unsupervised features are extracted automatically using a DCNN from the BLM of SAVMD. The extracted distinct feature vector is fed to the proposed supervised OSRVFLN classifier to train accurately by minimizing the training cross-entropy loss with an increment in the number of hidden nodes for obtaining the maximum classification accuracy of the complex PQE patterns in noisy and noise-free environments. The automatic efficacious feature extraction, superior classification accuracy, noise immunity, and short event detection time are the major advantages of the proposed SAVMD-DCNN-OSRVFLN method. Finally, the novel methodology is implemented in a fast digital Xilinx Virtex-5 field-programmable gate array embedded processor to validate the practicability and feasibility of the proposed method in real-time.
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