期刊
IEEE TRANSACTIONS ON NUCLEAR SCIENCE
卷 68, 期 5, 页码 611-616出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TNS.2021.3053168
关键词
Ions; Logic gates; MOSFET; Silicon; Electric fields; Transient analysis; Semiconductor process modeling; Heavy ion; power MOSFET; single-event gate rupture (SEGR); super-junction (SJ); technology computer-aided design (TCAD) analysis; VDMOS
资金
- Defense Threat Reduction Agency (DTRA) [HDTRA1-17-1-0038]
This article compares and analyzes the single-event gate rupture (SEGR) response of silicon planar gate super-junction (SJ) power metal oxide semiconductor field effect transistors (MOSFETs) and vertical double diffused power MOSFETs (VDMOSs). The study shows that SJMOS has better SEGR tolerance than VDMOS for heavy-ion strikes at different angles.
This article compares and analyzes the single-event gate rupture (SEGR) response of silicon planar gate super-junction (SJ) power metal oxide semiconductor field effect transistors (MOSFETs) and vertical double diffused power MOSFETs (VDMOSs). When an incident heavy-ion strike is perpendicular to the gate oxide, the SEGR tolerances of SJ power MOSFETs (SJMOSs) and VDMOSs are similar. But, for heavy-ion strikes that are at different angles, SJMOS has better SEGR tolerance than VDMOS. This improved performance of SJMOS is due to the presence of an additional horizontal electric field component in SJMOS devices. This is validated using the experimental data and simulation results in this article.
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