期刊
IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS
卷 57, 期 3, 页码 3107-3119出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TIA.2020.3002182
关键词
Topology; Capacitors; Switches; Inverters; Turning; Electrical engineering; Stress; Boost topology; multilevel inverter (MLI); reduce switch count; selective harmonic elimination pulsewidth modulation (SHEPWM); switched-capacitor (SC)
资金
- University of Malaya, Malaysia, under Impact Oriented Interdisciplinary Research Grant (IIRG) [IIRG011A2019]
- Ministry of Higher Education, Malaysia, under Large Research Grant Scheme (LRGS) [LR008-2019]
The article introduces a new switched-capacitor-based boost multilevel inverter topology, capable of generating a high-quality output waveform with multiple features and functions. The performance and effects of the proposed multilevel inverter are validated through experiments conducted with a laboratory prototype setup.
Multilevel inverter (MLI) topologies play a crucial role in the dc-ac power conversion due to their high-quality performance and efficiency. This article aims to propose a new switched-capacitor-based boost multilevel inverter topology (SCMLI). The proposed topology consists of nine power semiconductor switches with one dc voltage source and two capacitors, capable of generating a nine-level output voltage waveform with twice voltage gain. With the addition of two switches, the proposed topology can be used for higher voltage-gain applications. Other features of the proposed topology include the self-voltage balancing of the capacitors, parallel operation of the capacitors, lower voltage stress across the switches, along with the inherent polarity changing capability. To obtain the high-quality output waveform, a selective harmonic elimination pulsewidth modulation technique is applied. In this technique, the detrimental low-order harmonics can easily be regulated and eliminated from the output voltage of MLI. The proposed topology is compared with the recently introduced SCMLI topologies considering various parameters to set the benchmark of the proposed topology. The performance of the proposed MLI is investigated through various experimental results using a laboratory prototype setup.
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