期刊
IEEE TRANSACTIONS ON ELECTRON DEVICES
卷 68, 期 4, 页码 1585-1592出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2021.3058199
关键词
Nonvolatile memory; Programming; Stress; Logic gates; IP networks; Decoding; Writing; 2T-SONOS; disturbance; embedded nonvolatile memory (NVM)
资金
- [10041855]
A 32 kB embedded nonvolatile memory (NVM) IP using 2T-SONOS cells was developed, but abnormal memory cell failure was discovered during probe testing, mainly due to insufficient G-S disturbance immunity.
We developed a 32 kB embedded nonvolatile memory (NVM) intellectual property (IP) using 2T-SONOS cells. Although SONOS cells possess intrinsic defect immunity, we discovered abnormal memory cell failure during the probe test of the IP. The major failed items are checkerboard (CKBD), inverse CKBD, and gate-with-source (G-S) disturbance at the erased state. The threshold voltage distributions and electrical failure analysis (FA) reveal that all major failures occurred because of an abnormally weak G-S disturbance immunity. In addition, the temperature dependency of the G-S disturbance implies that the failure mechanism is related to Co-spike rather than midgap trap-induced junction leakage. Although abnormal defects are not detected through physical FA, by using simple failure modeling and a process split test, we verified the root cause of a new type of erratic failure. The single-bit disturbance failure can be explained as electrons generated in the floating junction area being accelerated in the G-S stress mode, resulting in soft programming by the channel hot electron (CHE) injection mechanism.
作者
我是这篇论文的作者
点击您的名字以认领此论文并将其添加到您的个人资料中。
推荐
暂无数据