4.6 Article

Characteristics of InAs/GaSb Line-Tunneling FETs With Buried Drain Technique

期刊

IEEE TRANSACTIONS ON ELECTRON DEVICES
卷 68, 期 4, 页码 1537-1541

出版社

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2021.3059391

关键词

Tunneling; TFETs; Metals; Leakage currents; Semiconductor process modeling; Logic gates; Photonic band gap; Buried drain technique; InAs; GaSb; line-tunneling; tunneling field effect transistor (TFETs)

资金

  1. Applied Basic Research Plan of Shanxi Province [201901D211400]
  2. National Natural Science Foundation of China [62004119]

向作者/读者索取更多资源

The combination of InAs/GaSb heterojunction and the line-tunneling mechanism is a promising approach for achieving high ON-state current and low subthreshold swing in TFETs. By introducing an N+ doped buried drain to form a reverse biased p-n junction, leakage current path can be effectively cut off in InAs/GaSb LTFETs, resulting in excellent performance without additional fabrication complexity.
The combination of the InAs/GaSb heterojunction and the line-tunneling mechanism is considered as one of the most promising approaches to simultaneously obtain high ON-state current (I-ON) and low subthreshold swing (SS) in tunneling field effect transistors (TFETs). However, in an InAs/GaSb line-tunneling field effect transistor (LTFET), the isolation between the source and the drain is a big issue. The leakage current path could lead to complete loss of the OFF-state characteristics in extreme cases. The cantilever or airbridge structure is usually introduced to cutoff the leakage path. However, it also induces serious reliability problems and brings additional process complexity. In this article, an N+ doped buried drain is first proposed to form a reverse biased p-n junction with the P+ source and effectively cuts the leakage current path off. The InAs/GaSb LTFETs with this buried drain technique exhibits I-ON/I-OFF > 10(7) and SS < 60 mV/dec for five decades of current. Besides the excellent performance, the buried drain technique keeps the device planar and brings no additional fabrication complexity, which is of great significance for future experimental investigation and the low power applications.

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