Design Technology Co-Optimization for Back-End-of-Line Nonvolatile NEM Switch Arrays

Design tradeoffs for vertically oriented nonvolatile (NV) nano-electro-mechanical (NEM) switches implemented using multiple interconnect layers in a 5-nm-generation CMOS back-end-of-line (BEOL) process are investigated via 3-D device simulation. Programming pulse voltage and width operating windows are identified for avoiding catastrophic pull-in. The simulation results indicate that sub-20-ns programming delay is possible with programming voltages compatible with standard input-output (I/O) CMOS circuitry, and that the write energy of an NV-NEM bit-cell will be less than 5 aJ. A crossbar array architecture operated with a half-select row/column bit-cell programming scheme is found to be effective for avoiding the issue of write disturbance.

Automated summary

Design tradeoffs for vertically oriented nonvolatile (NV) nano-electro-mechanical (NEM) switches implemented using multiple interconnect layers in a 5-nm-generation CMOS back-end-of-line (BEOL) process are investigated via 3-D device simulation. It is found that sub-20-ns programming delay is possible with programming voltages compatible with standard input-output (I/O) CMOS circuitry, and that the write energy of an NV-NEM bit-cell will be less than 5 aJ. A crossbar array architecture operated with a half-select row/column bit-cell programming scheme is effective for avoiding write disturbance.