期刊
IEEE JOURNAL OF SOLID-STATE CIRCUITS
卷 56, 期 4, 页码 1046-1057出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2020.3037833
关键词
Analog-to-digital converter (ADC); background calibration; differential pulse-code modulation (DPCM); noise shaping; sensor front end; sensor readout; voltage-controlled oscillator (VCO)
The design utilizes DPCM compression theory to substantially reduce the signal amplitude incident to the VCO quantizer, achieving ultra-low THD. Background digital gain calibration and dynamic element matching (DEM) techniques ensure robustness and high efficiency in achieving a high DR.
This article presents a high-dynamic-range (DR) voltage-controlled oscillator (VCO)-based front end for sensor readout applications. Unlike conventional VCO-based quantizers, which suffer from large voltage-to-frequency non-linearities, the proposed design leverages differential pulse-code modulation (DPCM) from compression theory to substantially reduce the amplitude of the signal incident to the VCO quantizer, thereby achieving an ultra-low total harmonic distortion (THD) of -112 dB. In addition, background digital gain calibration is employed to overcome gain deviation of the VCO, thus ensuring a robust design. Together with dynamic element matching (DEM), the techniques enable a high DR using only the first-order noise shaping inherent in VCO-based quantizers and a moderate 32x oversampling ratio. Fabricated in 65 nm, the sensor front end consumes 3.2-mu W power and achieves an SNDR of 89 dB and a DR of 94 dB in 500 Hz of bandwidth. Together with a 1.18-mu V-rms integrated input-referred noise, it achieves a noise efficiency factor (NEF) of 4 and a Schreier FoM of 171 dB.
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