期刊
CIRCUITS SYSTEMS AND SIGNAL PROCESSING
卷 40, 期 7, 页码 3305-3337出版社
SPRINGER BIRKHAUSER
DOI: 10.1007/s00034-020-01620-6
关键词
EEG; Power line interference; Adaptive filter; CMOS VLSI design
资金
- CNPq
- Capes
- Fapergs
Electroencephalogram (EEG) is a key biomedical technique for capturing electrical information of the human brain. Challenges in EEG system design include ultra-low signal amplitude and susceptibility to interference. Investigation into adaptive filtering techniques for protecting against interference shows normalized LMS filters offer the best tradeoff between eliminating noise and energy consumption.
Electroencephalogram (EEG) is a biomedical technique for capturing the human brain's electrical information to process its activities and actions. EEG is one of the main methods commonly used in neuroscience, from clinical analysis to the design of brain-computer interfaces. The first one of the many challenges in an EEG system design regards the ultra-low amplitude of signals (i.e., of the order of 20 mu V) and their susceptibility to several kinds of interferences. Electromagnetic interference (EMI) omnidirectionally irradiated by the power line supplies disturbs the EEG instrumentation system with a noise power mostly concentrated from 50 to 60 Hz. Our paper investigates the energy efficiency of adaptive filtering (AF) techniques based on the least mean square (LMS), normalized LMS, and set-membership (SM) families for meeting the protection against EMI in EEG systems. The results demonstrate that the LMS algorithm presents an unstable behavior with unsatisfactory results against the normalized LMS filters when subject to noisy scenarios. Therefore, we herein explore dedicated VLSI hardware architectures for the following filters: (a) normalized LMS (NLMS), (b) SM-NLMS, (c) partial update NLMS (PU-NLMS), and (d) SM bi-normalized LMS (SM-BNLMS). PU-NLMS architecture offers the best tradeoff between the capability of eliminating the EMI versus its power dissipation, circuit area, and maximum clock frequency. PU-NLMS provides an artifact reduction level of up to 8.8 dB, with low energy consumption of 0.62 nJ/operation and just 1.41% larger circuit area than the NLMS architecture.
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