In-Plane Monolithic Integration of Scaled III-V Photonic Devices

It is a long-standing goal to leverage silicon photonics through the combination of a low-cost advanced silicon platform with III-V-based active gain material. The monolithic integration of the III-V material is ultimately desirable for scalable integrated circuits but inherently challenging due to the large lattice and thermal mismatch with Si. Here, we briefly review different approaches to monolithic III-V integration while focusing on discussing the results achieved using an integration technique called template-assisted selective epitaxy (TASE), which provides some unique opportunities compared to existing state-of-the-art approaches. This method relies on the selective replacement of a prepatterned silicon structure with III-V material and thereby achieves the self-aligned in-plane monolithic integration of III-Vs on silicon. In our group, we have realized several embodiments of TASE for different applications; here, we will focus specifically on in-plane integrated photonic structures due to the ease with which these can be coupled to SOI waveguides and the inherent in-plane doping orientation, which is beneficial to waveguide-coupled architectures. In particular, we will discuss light emitters based on hybrid III-V/Si photonic crystal structures and high-speed InGaAs detectors, both covering the entire telecom wavelength spectral range. This opens a new path towards the realization of fully integrated, densely packed, and scalable photonic integrated circuits.

Automated summary

The article reviews various methods for monolithic III-V integration, with a focus on the results achieved using the TASE technique. This method enables self-aligned in-plane monolithic integration of III-V materials on silicon by selectively replacing pre-patterned silicon structures. The study discusses the realization of in-plane integrated photonic structures, particularly focusing on light emitters and high-speed detectors covering the telecom wavelength spectral range, which may lead to fully integrated, densely packed, and scalable photonic integrated circuits.