Nanowatt use 8 V switching nonvolatile memory transistors with 2D MoTe2 channel and ferroelectric P(VDF-TrFE)

Two dimensional (2D) p-MoTe2 channel-based nonvolatile memory transistors with ferroelectric P(VDF-TrFE) polymer has been studied using a bottom-gate device architecture, which is introduced to dramatically reduce both of the switching and drain voltages to minimum 8 V and 10 mV, respectively. In fact, most of 2D-channel ferroelectric FETs with the same P(VDF-TrFE) polymer have used top-gate architectures, utilizing high switching pulse voltages over 20-25 V due to the existence of dead layer, which is unavoidably formed at the interface between P(VDF-TrFE) and thermal-deposited Al top gate. Key effects to realize such a low 8-13 V switching thus originate from the bottom-gate architecture. On the one hand, keys to obtain the low operation/drain voltage come from anneal-free Ohmic contact which is obtained using H2O2 solution. Thanks to the low operation voltages of 10 mV, consuming power in the nonvolatile FETs can be minimized to similar to a few pW for OFF/Erase state and-a few hundred pW for ON/Program although it eventually becomes similar to nW and similar to 30 nW for OFF and ON states in a practical circuit operation to switch organic light emitting diodes. Our approaches of bottom-gate architecture and H2O2 contact nicely work even for transparent nonvolatile memory FET.

Automated summary

This study investigates two dimensional p-MoTe2 channel-based nonvolatile memory transistors with ferroelectric P(VDF-TrFE) polymer using a bottom-gate device architecture, which significantly reduces switching and drain voltages to minimize power consumption. By employing special processing methods and a bottom-gate structure, low-power memory transistors were successfully fabricated.