Multibit-RRAM readout circuits based on non-balanced inverters

The demand for electronic memories with increasing storage capabilities is always on the rise. Increasing the information density in the same silicon area is a desirable feature, making fast multilevel resistive switching devices a promising candidate. It is thus necessary to design writing and readout circuits that are able to take advantage of the technology's features. In this work, two multibit readout circuits based on non-balanced inverter are presented. The first one is a simple and size reduced flash-type ADC made of inverters, while the second one is a counter-type ADC circuit. Simulations were performed in 0.18 mu m CMOS technology using a memristor model extracted from bibliography in order to analyze and compare functionality, power consumption and speed access. The resulting reading time is lower than 1.5 ns for the flash-type ADC and 12 ns for the counter-type ADC. Regarding layout area, the core circuit of the first architecture was implemented in 165 mu m(2) and the second in 798 mu m(2).

Automated summary

Two multibit readout circuits based on non-balanced inverters were proposed in this study, including a flash-type ADC and a counter-type ADC. Simulations were conducted in 0.18 mu m CMOS technology, showing that the flash-type ADC has faster reading time while the counter-type ADC has larger layout area.