期刊
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
卷 29, 期 2, 页码 386-396出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TVLSI.2020.3042411
关键词
Hybrid integrated circuits; neural network; resistive random access memory (RRAM); three-dimensional integrated circuits
资金
- Semiconductor Research Corporation [2929]
- National Science Foundation [NSF-CCF-1903951]
The article presents the first-ever heterogeneous mixed-signal monolithic 3-D IC designs of the RRAM CNN accelerator, which overcome the bottleneck caused by ADCs and offer significant improvement in energy efficiency compared to traditional 2-D IC designs.
Resistive random access memory (RRAM)-based compute-in-memory architecture helps overcome the bottleneck caused by large memory transactions in the convolutional neural network (CNN) accelerators. However, their deployment using 2-D IC technology faces challenges, as today's RRAM cells remain at legacy nodes above 20 nm due to high programming voltages. Besides, power-hungry analog-to-digital converter (ADC) units limit the throughput of RRAM accelerators. In this article, we present the first-ever heterogeneous (multiple technology nodes) mixed-signal monolithic 3-D IC designs of the RRAM CNN accelerator. Our RRAM remains at legacy 40-nm nodes in one tier, but CMOS periphery scales toward advanced 28/16 nm in another tier. Our 3-D designs overcome the bottleneck caused by ADCs and offer up to 4.9x improvement in energy efficiency in TOPS/W and up to 50% reduction in footprint area over 40-nm 2-D IC designs. Compared with existing 2-D works, our 3-D architecture offers up to 28.6x improvement in energy efficiency.
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