Switching Performance Analysis of 3.5 kV Ga2O3 Power FinFETs

This article presents switching performance analysis of a normally-off 3.5 kV beta-Ga2O3 power FinFET using Silvaco TCAD simulation platform. The simulated electric field and OFF-state capacitances at a drain voltage (V-D) of 3.5 kV were compared for FinFETs with two different structures: (i) 30-nm-thick Al2O3 in the planar regions and partially-filled (PF) inter-fin areas and (ii) 130-nm-thick Al2O3 in the planar regions and fully-filled (FF) inter-fin areas. The FF FinFET showed a smaller OFF-state CGS and CGD and the thicker Al2O3 significantly reduced peak electric field at the corner of the fin. Therefore, via TCAD device-circuit-integrated model, the impact of electron mobility in the MOS channel, bulk fin and drift region, and the substrate thickness on the device switching performances were investigated on a single-fin FF FinFET structure. The device with 100-mu m-thick substrate and ideal drift region and fin mobilities of 180 cm(2)/Vs showed 82.6% improvement in the total switching time and 82.2% lower switching losses compared with the devicewhich had thicker substrate thickness (600 mu m) and lower electron mobilities in the drift region (130 cm(2)/Vs), bulk fin (30 cm(2)/Vs), and MOS channel (2 cm(2)/Vs). Moreover, the switching performance ofmultifin FF FinFETs with different fin width/pitch ratio was studied. At a given pitch size of 700 nm, the total power loss of the input power at a frequency of 200 kHz was reduced from 0.83% to 0.61% as pitch ratio reduced from 57.1% to 14.3%. These findings provide helpful insights for design and fabrication of Ga2O3 FinFETswith enhanced switching performance for low-waste power conversion applications.

Automated summary

This article analyzed the switching performance of a normally-off 3.5 kV beta-Ga2O3 power FinFET using Silvaco TCAD simulation platform. By comparing FinFETs with different structures, it was found that the fully-filled (FF) FinFET showed improved OFF-state capacitances and reduced peak electric field. Through TCAD simulations, it was determined that device performance could be significantly enhanced by optimizing substrate thickness and electron mobilities in different regions of the FinFET.