Stand-by Power Reduction Using Experimentally Demonstrated Nano-Electromechanical Switch in CMOS Technologies

In this article, we demonstrate a double-clamped nano-electromechanical switch (NEMS) with low stand-by power as an effective solution to the leakage issues in scaled CMOS-based power gating (PG) in logic circuits. The proposed NEMS structure is achieved to have a low pull-in (similar to 1.2 V), low hysteresis (<0.3 V), low turnon delay (35 ns), and subthreshold slope of <6 mV/decade. This enables reduction in stand-by power dissipation in sub 10-nm CMOS technologies with a narrow 100 nm dimple gap for the low-power NEMS. We illustrate that the PG in ISCAS'85 benchmark circuits using the proposed fabricated NEMS shows significant leakage energy reduction for T-ON/T-OFF < 0.01 as compared to the sub 10-nm CMOS based PG.

Automated summary

In this article, a double-clamped nano-electromechanical switch (NEMS) with low stand-by power is proposed as an effective solution to leakage issues in scaled CMOS-based power gating (PG) in logic circuits. The NEMS structure achieves low pull-in voltage, low hysteresis, low turn-on delay, and subthreshold slope, enabling reduction in stand-by power dissipation in sub 10-nm CMOS technologies. Experimental results demonstrate significant leakage energy reduction compared to sub 10-nm CMOS based PG in ISCAS'85 benchmark circuits.