Algorithmic-Level Approximate Tensorial SVM Using High-Level Synthesis on FPGA

Approximate Computing Techniques (ACT) are promising solutions towards the achievement of reduced energy, time latency and hardware size for embedded implementations of machine learning algorithms. In this paper, we present the first FPGA implementation of an approximate tensorial Support Vector Machine (SVM) classifier with algorithmic level ACTs using High-Level Synthesis (HLS). A touch modality classification framework was adopted to validate the effectiveness of the proposed implementation. When compared to exact implementation presented in the state-of-the-art, the proposed implementation achieves a reduction in power consumption by up to 49% with a speedup of 3.2x. Moreover, the hardware resources are reduced by 40% while consuming 82% less energy in classifying an input touch with an accuracy loss less than 5%.

Automated summary

This paper presents the first FPGA implementation of an approximate tensorial Support Vector Machine classifier using High-Level Synthesis, with a touch modality classification framework to validate its effectiveness. Compared to exact implementations, the proposed approach achieves up to 49% reduction in power consumption, 3.2x speedup, 40% reduction in hardware resources, and 82% less energy consumption while maintaining an accuracy loss of less than 5% when classifying input touch data.