CMOS-compatible ferroelectric NAND flash memory for high-density, low-power, and high-speed three-dimensional memory

Ferroelectric memory has been substantially researched for several decades as its potential to obtain higher speed, lower power consumption, and longer endurance compared to conventional flash memory. Despite great deal of effort to develop ferroelectric memory based on perovskite oxides on Si, formation of unwanted interfacial layer substantially compromises the performance of the ferroelectric memory. Furthermore, three-dimensional (3D) integration has been unimaginable because of high processing temperature, non-CMOS compatibility, difficulty in scaling, and complex compositions of perovskite oxides. Here, we demonstrate a unique strategy to tackle critical issues by applying hafnia-based ferroelectrics and oxide semiconductors. Thus, it is possible to avoid the formation of interfacial layer that finally allows unprecedented Si-free 3D integration of ferroelectric memory. This strategy yields memory performance that could be achieved neither by the conventional flash memory nor by the previous perovskite ferroelectric memories. Device simulation confirms that this strategy can realize ultrahigh-density 3D memory integration.

Automated summary

Ferroelectric memory has been extensively researched for its potential of higher speed, lower power consumption, and longer endurance compared to conventional flash memory. By utilizing hafnia-based ferroelectrics and oxide semiconductors, it is possible to avoid unwanted interfacial layers and achieve unprecedented Si-free 3D integration of ferroelectric memory, with memory performance surpassing conventional flash memory and previous perovskite ferroelectric memories.