Enhanced Electrical Performance of Van der Waals Heterostructure

In this study, a novel van der Waals (vdW) heterostructure field-effect transistor (FET) using vdW stacking as next-generation device architecture is demonstrated. The MoS2/WS2 heterostructure FET exhibits a large improvement in the drain current and field-effect mobility (from 43.3 to 62.4 cm(2) V-1 s(-1)) compared with single MoS2 FET. Such significant enhancement is mainly due to the charge-transfer effect. The vdW self-encapsulation effect in the device channel also helps to reduce the Schottky barrier height from 120 to 52 meV at the contact interface. Finally, the WS2/MoS2/WS2 double heterostructure FETs further boosts the mobility up to 102.5 cm(2) V-1 s(-1) at room temperature (25 degrees C) and 169.7 cm(2) V-1 s(-1) at 30 K. The much higher mobility exhibited at the lower temperature indicates the suppression of Coulomb scattering. Thus the electrical performance of the double-heterostructure FETs can be further enhanced.

Automated summary

A novel van der Waals heterostructure field-effect transistor using van der Waals stacking as the next-generation device architecture is demonstrated in this study. The MoS2/WS2 heterostructure FET shows significant improvement in drain current and field-effect mobility mainly due to charge-transfer effect, as well as reduction in Schottky barrier height at the contact interface. The WS2/MoS2/WS2 double heterostructure FETs further enhance mobility at both room temperature and lower temperature, indicating potential for further enhanced electrical performance.