Elliptical nanowire FET: Modeling the short-channel subthreshold current caused by interface-trapped-charge and its evaluation for subthreshold logic gate

Based on the quasi-3D potential approach, quasi-3D scaling theory, drift-diffusion model, and equivalent flat-band voltage shift, a short-channel subthreshold current caused by the interfacetrapped-charge is modeled for the elliptical nanowire FET. With the subthreshold current, the logic swing (LS) of the subthreshold logic gate composed of elliptical nanowire FET is theoretically evaluated. It indicates that the positive interface-trapped-charge can degrade the high output voltage (V-OH) due to its increased/decreased the subthreshold current of N-FET/P-FET. However, the negative interface-trapped-charge can decrease/increase the subthreshold current of N-FET/P-FET, which hence deteriorates the low output voltage (V-OL). Both degradation of the subthreshold current and LS (i.e., Delta I-sub and Delta LS) caused by short-channel effects (SCEs) can be well-controlled by the properly selected scaling factor of alpha. With the minimum scaling factor, the minimum LS degradation for the subthreshold logic gate can be uniquely determined.

Automated summary

A model for short-channel subthreshold current in elliptical nanowire FETs caused by interface-trapped charge was established using quasi-3D potential approach and drift-diffusion model. The positive and negative interface-trapped charges were found to degrade the high and low output voltages of N-FET/P-FET, respectively. Short-channel effects on subthreshold current and logic swing can be controlled by selecting the scaling factor, with the minimum factor uniquely determining the minimum LS degradation for the subthreshold logic gate.