Design of Efficient Reverse Converters for Residue Number System

The main factors that affect the performance of residue number system (RNS) are speed and hardware complexity of the residue-to-binary converter. In this paper, two efficient reverse converters are proposed for the moduli sets {2(2n-1)-1, 2(n)-1, 2(n)+1, 2(n)} and {2(2n-1)-1, 2(n)-1, 2(n)+1, 22(n-1)} based on two-level approach. In the first level, a reverse converter is implemented based on new Chinese remainder theorem-I for the moduli set {2(2n-1)-1, 2(n)-1, 2(n)+1}. The fourth modulus is joined in the second level for each converter and only simple binary adders are used in this level. The architecture of novel circuits mainly consists of simple adders thus leading to implementing efficient converters. To have a fair comparison, both unit gate model and simulation are used. The proposed converters and the recently represented converters have been implemented on Xilinx ISE 13.1 field-programmable gate array (FPGA) simulator to derive area and delay that are measured for the various ranges up to 256 bits. The experimental results show that the proposed converters have lower area-time complexity comparing to the state-of-the-art converter for similar moduli sets.

Automated summary

This paper proposes two efficient reverse converters based on a two-level approach for specific moduli sets, implemented using new algorithms and experimentally validated on the Xilinx ISE 13.1 FPGA simulator. Experimental results demonstrate that the proposed converters have lower area-time complexity compared to existing converters for similar moduli sets.