期刊
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
卷 39, 期 10, 页码 2434-2447出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCAD.2019.2931188
关键词
Logic gates; Throughput; Memristors; Tools; Logic functions; Arrays; Logic design; logic synthesis; memristor-aided logic (MAGIC); memristive systems; memristor; memristive memory-processing unit (mMPU); throughput; von Neumann architecture
类别
资金
- European Research Council under the European Union [757259]
- Israel Science Foundation [1514/17]
- European Research Council (ERC) [757259] Funding Source: European Research Council (ERC)
In-memory processing can dramatically improve the latency and energy consumption of computing systems by minimizing the data transfer between the memory and the processor. Efficient execution of processing operations within the memory is therefore, a highly motivated objective in modern computer architecture. This article presents a novel automatic framework for efficient implementation of arbitrary combinational logic functions within a memristive memory. Using tools from logic design, graph theory and compiler register allocation technology, we developed synthesis and in-memory mapping of logic execution in a single row (SIMPLER), a tool that optimizes the execution of in-memory logic operations in terms of throughput and area. Given a logical function, SIMPLER automatically generates a sequence of atomic memristor-aided logic (MAGIC) NOR operations and efficiently locates them within a single size-limited memory row, reusing cells to save area when needed. This approach fully exploits the parallelism offered by the MAGIC NOR gates. It allows multiple instances of the logic function to be performed concurrently, each compressed into a single row of the memory. This virtue makes SIMPLER an attractive candidate for designing in-memory single instruction, multiple data (SIMD) operations. Compared to the previous work (that optimizes latency rather than throughput for a single function), SIMPLER achieves an average throughput improvement of 435x. When the previous tools are parallelized similarly to SIMPLER, SIMPLER achieves higher throughput of at least 5x, with 23x improvement in area and 20x improvement in area efficiency. These improvements more than fully compensate for the increase (up to 17% on average) in latency.
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