Noise Optimization Techniques for Switched-Capacitor Based Neural Interfaces

This paper presents the noise optimization of a novel switched-capacitor (SC) based neural interface architecture, and its circuit demonstration in a 0.13 mu m CMOS process. To reduce thermal noise folding ratio, and suppress kT/C noise, several noise optimization techniques are developed in the proposed architecture. First, one parasitic capacitance suppression scheme is developed to block noise charge transfer from parasitic capacitors to amplifier output. Second, one recording path-splitting scheme is proposed in the input sampling stage to selectively record local field potentials (LFPs), extracellular spikes, or both for reducing input noise floor, and total power consumption. Third, an auto-zero noise cancellation scheme is developed to suppress kT/C noise in the neural amplifier stage. A prototype neural interface chip was fabricated, and also verified in both bench-top, and In-Vivo experiments. Bench-top testings show the input-referred noise of the designed chip is 4.8 mu V from 1 Hz to 300 Hz, and 2.3 mu V from 300 Hz to 8 kHz respectively, and In-Vivo experiments show the peak-to-peak amplitude of the total noise floor including neural activity, electrode interface noise, and the designed chip is only around 20 mu V. In comparison with conventional architectures through both circuit measurement and animal experiments, it is well demonstrated that the proposed noise optimization techniques can effectively reduce circuit noise floor, thus extending the application range of switched-capacitor circuits.