期刊
IEEE JOURNAL OF SOLID-STATE CIRCUITS
卷 55, 期 9, 页码 2478-2488出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2020.2993672
关键词
Impedance; Routing; Bandwidth; Resistors; Timing; Distortion; Transistors; Compensation; current steering; digital-to-analog converter (DAC); layout arrangement; output impedance; timing skew
资金
- Ministry of Science and Technology (MOST) of Taiwan
A digital-to-analog converter (DAC) with small-size non-cascoded current cells is proposed to achieve small area, low-power consumption, and high linearity over a wide bandwidth. An output impedance compensation (OIC) technique using a compensation resistor, implemented by a PMOS with code-dependent gate voltage control, is proposed to remedy the nonlinearity induced by the insufficient output impedance of the non-cascoded current cells. In addition, a proposed concentric parallelogram routing (CPR) technique, in which the subcells of each current cell are arranged such that they form a parallelogram shape with a common centroid, is used to reduce both the mismatch error and the routing-induced timing skew among the current cells. The DAC, implemented in a 28-nm CMOS process, achieves >65-dBc spurious-free dynamic range (SFDR) and < -70-dBc third-order intermodulation distortion (IM3) over the entire Nyquist bandwidth at 10 GS/s while consuming 162 mW from a single 1.1 V supply.
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