High-performance and single event double-upset-immune latch design

This Letter proposes a single event double-upset (SEDU)-fully-tolerant latch, referred to as FBSET, mainly featuring four interlocked branch circuits implemented by stacking three PMOS and one NMOS transistors or three NMOS and one PMOS transistors to achieve low power dissipation. The latch exhibits up to 84.56% area-power-delay product saving compared with recently reported latches. Simulation results validate that the proposed latch is completely immune to SEDU.