Low Lattice Mismatch InSe-Se Vertical Van der Waals Heterostructure for High-performance Transistors via Strong Fermi-Level Depinning

Contact engineering, especially at the interface between metal and 2D semiconductors, to enable high-performance devices remains a formidable challenge due to the inevitable chemical disorder and Fermi-level pinning at the interface. Here, the authors report the InSe-Se vertical van der Waals (vdW) heterostructures to achieve high field-effect mobility and electrical stability in 30 nm InSe field-effect transistor (FET), which has a low lattice mismatch of 1.1% and form 2D/2D low-resistance contacts, creating an InSe contact interface that substantially limits chemical disorder and Fermi-level pinning. The Se layer forms a vdW contact to prevent the damage induced by direct metallization and acts as a tunneling layer as well as a protective encapsulation layer. Using this approach, heterojunction devices with a high field-effect mobility of approximate to 2500 cm(2) (V s)(-1) and an excellent on-state current of approximate to 10(-3) A at room temperature is achieved. Furthermore, the device field-effect mobility degrades by only 3.46% following two months of storage time in open air, which represents the best electrical stability reported to date. In particular, the heterojunction devices exhibit a better photoresponsivity compared with InSe devices in practical application. This study provides a highly valuable strategy to improve the contact condition of metal/2D semiconductors for high-performance, 2D-based electronics and optoelectronics.