期刊
PHYSICAL REVIEW APPLIED
卷 14, 期 2, 页码 -出版社
AMER PHYSICAL SOC
DOI: 10.1103/PhysRevApplied.14.024016
关键词
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资金
- National Natural Science Foundation of China [11904409, 11664026, 51572296, U1662113]
- Ministry of Science and Technology of China [2016YFB0700600]
- Fundamental Research Funds for the Central Universities [19CX05002A, 15CX08005A, 17CX06029]
- China Postdoctoral Science Foundation [2018M642721]
- Shandong Postdoctoral Funded Project [201901012]
As one of the thinnest forms of semiconducting silicon, monolayer (ML) silicane has not only excellent gate electrostatics and carrier transport ability, but also compatibility with well-established silicon-based technology. We explore the device performance limits of sub-5-nm ML silicane metal-oxide-semiconductor field-effect transistors (MOSFETs) by applying ab initio quantum transport simulations. The on-state current, effective delay time, and power-delay product of the optimized n-type andp -type ML silicane MOSFETs can well or nearly meet the high-performance device requirements of the International Technology Roadmap for Semiconductors (ITRS) at a gate length of 5 nm. Those of the optimized n-type ML silicane MOSFETs at a gate length of 3 nm and the p -type ML silicane MOSFETs at a gate length of 5 nm can meet the low-power-device demands of the ITRS. Thus, ML silicane as channel materials can scale the Moore's law down to 5 nm.
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