Hierarchical Design of a Secure Image Sensor with Dynamic Reconfiguration

This paper presents a secure reconfigurable hierarchical hardware architecture at the pixel and region level for smart image sensors to accelerate machine vision applications. The design maintains hierarchical processing that begins at the pixel level. It aims to reduce the computational burden on the sequential processor and increases the confidentiality of the sensor. We achieve this goal by preprocessing the data in parallel with event-based processing within the sensor and extract the local features, which are then forwarded to an encryption module. After that, an external processor can obtain the encrypted features to complete the vision application. This approach significantly accelerates the vision application by executing the low-level and mid-level image processing applications and simultaneously by reducing the data volume at the sensor level. The secure hardware architecture enables the vision application to perform in real-time with reliability. This hierarchical processing breaks the traditional sequential image processing and introduces parallelism for machine vision applications. We evaluate the design in FPGA and achieve the GDSII file in the ASIC platform at 800MHz. Simulation results show that the area overhead and power penalty for adding reconfiguration features stay in an acceptable range. Besides, removing redundant information, 84.01%, and 94.31% dynamic power can be saved at each pixel-level and region-level, respectively.