Design of low power approximate floating-point adders

Due to the increasing demands for more power in data intensive computing, low power design methodologies play a very important role in these systems. For noncritical data, the approximate computing that significantly reduces the power can be used. In this paper, an approximate floating-point adder is proposed by designing an inexact mantissa adder and exponent subtractor. The results indicate that the power consumption and delay of the proposed approximate floating-point adder have been decreased by 37% and 62% compared with the IEEE-754 single-precision floating-point (FP) adder. Furthermore, compared with a state-of-the-art inexact floating-point adder, the proposed method provides an improvement of 7% and 21% in terms of the power consumption and delay. In addition, the proposed floating-point adder has been investigated in terms of error, and the mean error of the proposed floating-point adder at worst is about 55% less than that of another approximate floating-point adder considered in this work. High dynamic range (HDR) images are processed using the proposed approximate floating-point adders to show the performance of the proposed adder. The results show that, on average, peak signal-to-noise ratio increased by 9.6 and 18.64 dB, which may be achieved by utilizing the proposed floating-point adder.

Automated summary

This paper proposes an approximate floating-point adder by designing inexact mantissa adder and exponent subtractor to reduce power consumption and delay. Experimental results show that the proposed method reduces power consumption and delay by 37% and 62% compared to IEEE-754 single-precision floating-point adder.