期刊
IEEE TRANSACTIONS ON POWER ELECTRONICS
卷 35, 期 8, 页码 8638-8651出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TPEL.2019.2962964
关键词
AC-AC conversion; back-to-back converter; com-mon-mode voltage; neutral point voltage; pulsewidth modulation; silicon carbide; three-level converter
资金
- Office of Energy Efficiency and Renewable Energy, U.S. Department of Energy [DEEE0006521]
- North Carolina State University, Power America Institute
In this article, a pulsewidth modulation (PWM) scheme for three-level full-SiC uninterruptible power supplies is developed to achieve a high power density. Two key passive components are selected for size reduction of the ac-ac stage: common-mode (CM) EMI filter, and dc-link capacitors. To reduce the CM noise, a new vector combination is proposed based on synchronous switching among three-phases. The proposed combinations align CM voltage (CMV) to be a single pulse per switching period. Owing to the simple shape, CMV cancellation between a three-level rectifier and inverter can be maximally utilized. A transition between the three combinations can control the drift of neutral point voltage. An equivalent carrier-based implementation is developed. Second, a simple algorithm to compensate neutral point voltage fluctuation is proposed both for differential mode (DM) and CM output voltage. Low-order harmonics on three-phase currents and an additional high-frequency CM noise by misaligned switching instant can be eliminated. The proposed compensation can be implemented by a simple correction on carrier slopes and injected zero-sequence voltage. The proposed PWM scheme is verified with 20-kW full-SiC UPS switching at 60 kHz with 140 mu F dc-link capacitors.
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