On the design of robust, low power with high noise immunity quaternary circuits

In this paper a design for Standard Quaternary Inverter (SQI) in Carbon Nanotube Field-Effect-Transistor (CNFET) technology is proposed. The proposed design is evaluated and compared with well-known designs. Therefore, several figures of merit (FOM) including maximum delay time, power consumption, Power-Delay-Product (PDP), count of utilized CNFETs and area occupation have been derived. Based on the simulation results in HSpice with standard 32 nm CNFET Stanford model, the proposed SQI is superior in terms of power consumption and PDP over other designs by roughly 50% and 150%, respectively. Furthermore, the noise margin is 19% higher than best values of other designs. For evaluating the robustness and capability, the PVT analysis and simulation of driving power and frequency-based performance of the designs were conducted. Based on the proposed SQI, the Quaternary NAND (QNAND), Quaternary NOR (QNOR) gates, Half Adder (HA) and Multiplier cells have been designed, simulated and evaluated as well. The results depict appropriate performance of designs.