Investigation of DC, RF and linearity performances of a back-gated (BG) heterojunction (HJ) TFET-on-selbox-substrate (STFET): Introduction to a BG-HJ-STEFT based CMOS inverter

This manuscript reports the back-gate effects on device-level performance of a heterojunction TFET on SELBOX substrate (HJ-STFET). The proposed structure implements a stacked gate oxide where the conventional SiO2 is replaced by a SiO2/HfO2 in a stacked manner to increase its On-current. A back gate (BG) is also considered in the proposed TFET to enhance the device-level performance. Investigation of DC, RF and linearity parameters such as drain current, transconductance, electric field, parasitic capacitance, cut-off frequency (f(T)), gain bandwidth product (GBP), intrinsic delay (tau), higher-order of g(m) (g(m2), g(m3)), VIP2, VIP3, IIP3, IMD3, and 1-dB compression point are carried out for the proposed TFET and the results are compared with other conventional structures. Performance evaluation shows that BG-HJ-STFET is a suitable candidate for distortionless and high-frequency applications. In addition, analysis of DC and transient behaviour of a CMOS TFET inverter using the BG-HJ-STFET is thoroughly investigated to verify its circuit-level performance.