4.6 Article

112-Gb/s PAM4 ADC-Based SERDES Receiver With Resonant AFE for Long-Reach Channels

期刊

IEEE JOURNAL OF SOLID-STATE CIRCUITS
卷 55, 期 4, 页码 1077-1085

出版社

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2019.2959511

关键词

112 Gb; s; analog-to-digital converter (ADC); feed-forward equalizer (FFE); PAM4; SAR; serializer; de-serializer transceiver (SERDES)

资金

  1. Intel

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A 112-Gb/s PAM4 analog-to-digital converter (ADC)-based serializer/de-serializer transceiver (SERDES) receiver is implemented on Intel's 10-nm FinFET process. The receiver consists of a low-noise resonant analog front end (AFE) which provides equalization and gain at 28 GHz, a 64-way time-interleaved ADC, digital equalization consisting of a 16-tap feed-forward equalizer (FFE), and a 1-tap decision-feedback equalizer (DFE), as well as a clock and data recovery (CDR) loop utilizing a 7-GHz digitally controlled oscillator (DCO). Long-reach, -35 dB Nyquist channels are supported by a pre-forward error correction (FEC) bit error rate (BER) of 1e-6, thus making it compatible with existing and projected IEEE Ethernet specifications.

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