Evaluating a Methodology for Designing CNFET-Based Ternary Circuits

A methodology for designing ternary circuits is proposed and evaluated. The method is based on a schema that consists of voltage levels, conditional blocks and weighting elements. The main idea is selecting appropriate voltage levels in conditional blocks and weighting them to generate desired output. In fact, the diagram is a framework for designing ternary logic gates. Hence, the optimum design can be accomplished by choosing the proper strategy particularly in conditional blocks. This could lead to minimum count of elements and decrement in complexity of the circuit. To examine the efficiency of the proposed method, three designs for standard ternary inverter (STI), ternary NAND (TNAND) and ternary NOR (TNOR) gates in carbon nanotube field-effect-transistor (CNFET) technology are presented, respectively. Several simulations are done using Synopsys HSPICE tool in 32 nm CNFET technology to measure the performance parameters for proposed designs and state-of-the-art CNFET-based designs. Moreover, the robustness of STIs in different operational conditions such as variations frequency and output load, and their senility to process deviations are measured. The simulation is done for TNAND, TNOR and half adder cell as well. The results demonstrate the proper functionality of the proposed methodology. Moreover, the designed circuits benefit from the minimum count of CNFETs, least maximum equivalent input capacitor, minimum variety of CNT diameters and delay time, while its pdp is very close to best results in comparison with state-of-the-art designs.