Abnormal threshold voltage shift caused by trapped holes under hot-carrier stress in a-IGZO TFTs

In the investigation of the reliability of a back-channel-etching type amorphous InGaZnO thin film transistor, we found that hot carrier stress has caused an abnormal parallel negative threshold voltage shift in the I-D-V-G measurement. An electrical measurement method named drain stress was established to investigate this instability. Through the analysis of recovery behavior, gate bias stress and Silvaco simulation, we confirmed that holes from the drain side inject into the passivation layer and/or back-channel interface region rather than into the gate insulator under the transverse electric field. A physical model is proposed to verify this electrical degradation behavior. This work demonstrates that drain stress is valuable in examining the quality of the passivation layer in thin film transistors.