期刊
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING
卷 33, 期 1, 页码 53-61出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TSM.2019.2957508
关键词
Semiconductor device modeling; Integrated circuit modeling; Mathematical model; Measurement uncertainty; Error correction; Semiconductor device measurement; Lithography; Overlay error modeling; wafer-level model; field-by-field model; ridge regression; hybrid model
类别
资金
- SK Hynix Company Ltd.
- National Research Foundation of Korea (NRF) - Korea Government (MSIT) [NRF-2019R1A2B5B01070358]
Overlay modeling, which predicts and corrects the overlay errors of wafers in the photolithography process, is emerging as a key technology for yield improvement. An overlay error is defined as a misalignment between the circuit images of the current and preceding exposure layers. Overlay modeling is classified into wafer-level modeling, which creates a single regression equation to correct the overlay errors of the entire wafer, and field-level modeling, which prepares a regression equation for each field of the wafer to conduct field-by-field error corrections. However, the former does not fully reflect the overlay error signatures of the fields, while the latter has an overfit problem with overlay errors in the fields used in model training. This paper proposes a hybrid modeling that creates field-by-field error prediction models by using an ensemble of ordinary least squares (OLS) regression and ridge regression to consider the wafer-level and field-level overlay error signatures, respectively. The hybrid modeling can appropriately reflect the overlay error signature of each field while avoiding the overfitting issue. The experimental results using field photolithography process data show that the mean squared error of the hybrid model was improved by 15.9% compared to that of the OLS regression-based model.
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