Device and Circuit-Level Assessment of GaSb/Si Heterojunction Vertical Tunnel-FET for Low-Power Applications

This article investigates the performance of a vertically grown GaSb/Si tunnel field effect transistor (V-TFET) with a source pocket to enhance the performance of the device. The commercially available Silvaco TCAD has been used for simulating the proposed V-TFET structure. A low bandgap material, GaSb, is used in the source region for the first time to enhance the carrier tunneling through the source (GaSb)-channel (Si) heterojunction. The proposed V-TFET with a pocket shows the improved subthreshold swing (SS) of 26 mV/decade at V-DS = 0.5 V over the V-TFET without any pocket. The effects of temperature on SS and I-ON/I-OFF ratio along with the analog/RF figures of merit (FOMs) are also analyzed for V-TFETs with and without a pocket. The results are also compared with some recently reported TFETs. The dc and analog/RF performances of V-TFET with a pocket are shown to be better than those of the V-TFET without a pocket and other reported TFET structures. Finally, the applications of V-TFETs with and without a pocket in designing inverter and ring oscillator circuits have been demonstrated. The dc and transient responses of the V-FET-based inverter and ring oscillator circuits have been analyzed using the Verilog-A model in the CADENCE tool.