A novel thermal management scheme for 3D-IC chips with multi-cores and high power density

To solve the increasingly serious thermal management problem of chips with multi-cores and high power density in the three-dimensional integrated circuit (3D-IC), a model of 3D-IC interlayer microchannel structure is developed to analyze the temperature distribution on the bottom of the processor and flow field distribution inside the microchannel. Moreover, based on the real structure of Intel's sixth generation microprocessor, four cores with an arrangement of 2 x 2 are involved in the processor of the present model. As the results, the effects of micro-pin fin width and arrangement, clustered micro-pin fins on the core regions and baffles on the surrounding region are discussed on the maximum temperature in the core regions and the total pressure drop of the microchannel heat sink. The numerical results prove that two peaks present on the surface temperature along the flow direction, which attributes to the higher heat flux of the core regions. However, clustering micro-pin fins on the core regions deteriorate the heat transfer performance of chips, owing to the increase of flow resistance. By contrast, arranging in-line & staggered micro-pin fins on the core regions and adding single-layer baffles on the surrounding region are effective ways to balance the pumping power and heat transfer performance of the microchannel. After structural optimization the maximum temperature in the core areas decreases 8 K, correspondingly, the pumping power increases 148%.