Experimental investigation of buffer traps physical mechanisms on the gate charge of GaN-on-Si devices under various substrate biases

The gate charge change (Delta Q(g)) of GaN-on-Si power devices subjected to different substrate biases has been investigated. On-wafer pulse-mode voltage stress measurement is examined to probe the physical insight of different trap mechanisms into Q(g) characteristics. Distinct injected electrons interacting with the buffer traps lead to a significant decrease (increase) in Q(g) under negative (positive) substrate bias. Different levels of degradation on Delta Q(gd) to Delta Q(gs) after stress under negative and positive substrate biases indicate uneven distribution of acceptor-like traps and uniform distribution of donor-like traps in the GaN buffer level. Using Arrhenius plots associated with the Delta Q(g) shift, three dominant buffer traps with activation energies of E-V + 0.542eV, E-C -0.604eV, and E-C -0.608eV are extracted.